Eligibility

CHIPS for America Fund Opportunities

Funding will be made available across three Notices of Funding Opportunity (“NOFOs”), two of which have been released as of November 2023. NOFO 1 incentivizes commercial fabrication facilities and larger supply chain projects ($300 million or greater) while NOFO 2 is a dedicated funding opportunity for smaller supply chain projects (less than $300 million). All applicants must document receipt of a state/local covered incentive from the project’s jurisdiction to be eligible to apply for the federal-level incentives.

	NOFO 1	NOFO 2
Total NOFO funding pool	Not specified	$500 million
Federal incentive options	Grants, loans, or loan guarantees Applicants may pursue a combination of incentives	Direct funding only (grants or cooperative agreements)
Direct funding amount limits	Up to 35% of capital expenditures	Up to 10% of capital expenditures Up to 20%-30% in rare circumstances Higher percentage = longer application processing time
Application process	Rolling basis Statement of Interest (“SOI”), pre-application, and full application	December 1, 2023-February 1, 2024 Concept Plan and invite-only full application

 

NOFO 3 is expected to be released in early 2024 and will focus on research and development projects.

Eligible Applicants

Eligible applicant types include a non-profit entity, a private-sector entity, a consortium of private-sector entities, or a consortium of non-profit, public, and private-sector entities with a demonstrated ability to substantially finance, construct, expand, or modernize a facility relating to fabrication, assembly, testing, advanced packaging, or production of semiconductors, materials used to manufacture semiconductors, or semiconductor manufacturing equipment.

Eligible Projects	Ineligible Projects
Expand or modernize leading-edge, current-generation, or mature-node semiconductor fabrication or supply chain facilities Site development for facilities Workforce development and supportive services (e.g., training for facility staff or construction workers, childcare)	Relocation of existing domestic facility or equipment Facilities constructed outside of the U.S. Stock buy-backs or dividend payments Projects charging above actual costs incurred Funding, exports, or collaborations with “foreign entities of concern” for 10 years after the award

Definitions for eligible facility types are detailed below:

• Leading-edge facilities that utilize the most advanced front-end fabrication processes which achieve the highest transistor and power performance. For logic, this currently includes facilities that produce semiconductors at high volumes using extreme ultraviolet (EUV) lithography tools. For memory, this currently includes facilities capable of producing 3D NAND flash chips with 200 layers and above, and/or dynamic random-access memory (DRAM) chips with a half-pitch of 13 nm and below. 
• Current-generation facilities that produce semiconductors that are not leading edge, up to 28 nm process technologies, and include logic, analog, radio frequency, and mixed-signal devices. New and expanded current-generation front-end fabrication facilities will deliver manufacturing capacity for current-generation semiconductor technologies, as well as new and specialty technologies such as devices based on compound semiconductor materials.
• Mature-node facilities that fabricate generations of: (a) logic and analog chips that are not based on FinFET, post-FinFET transistor architectures, or any other sub-28 nm transistor architectures; (b) discrete semiconductor devices such as diodes and transistors; (c) optoelectronics and optical semiconductors; and (d) sensors.
• Back-end facilities for the assembly, testing, or packaging of semiconductors that have completed the front-end fabrication process. This category includes advanced packaging of semiconductors. The Department is particularly interested in these projects.
• Wafer manufacturing facilities for the high-volume production of semiconductor wafers, including wafers made from silicon, silicon carbide, and gallium nitride. These facilities are the sites of ingot production and wafer slicing, lapping, polishing, cleaning, and inspection.
• Semiconductor materials facilities for the manufacture or production, including growth or extraction, of materials used to manufacture semiconductors, which are the chemicals, gases, raw and intermediate materials, and other consumables used in semiconductor manufacturing. Specific examples include but are not limited to polysilicon; photoresists and ancillaries (developers, strippers, litho solvents, and anti-reflective and hardmask layers); sputter targets (including tantalum, titanium, and aluminum); and materials specifically used in quantum information systems (such as hafnium and niobium). Applications for the construction, expansion, or modernization of commercial semiconductor materials facilities will be eligible for this NOFO only if the capital investment, as defined in Section IV.I.7, equals or exceeds $300 million.
• Semiconductor manufacturing equipment facilities for the physical production of specialized equipment integral to the manufacturing of semiconductors and subsystems that enable or are incorporated into the manufacturing equipment. Specific examples of semiconductor manufacturing equipment include but are not limited to deposition equipment, including chemical vapor deposition, physical vapor deposition, and atomic layer deposition; etching equipment (wet etch, dry etch); lithography equipment (steppers, scanners, extreme ultraviolet); wafer slicing equipment, wafer dicing equipment, and wire bonders; inspection and measuring equipment, including scanning electron microscopes, atomic force microscopes, optical inspection systems, and wafer probes; certain metrology and inspection systems; and ion implantation and diffusion/oxidation furnaces. Applications for the construction, expansion, or modernization of commercial semiconductor equipment facilities will be eligible for this NOFO only if the capital investment, as defined in Section IV.I.7, equals or exceeds $300 million.

Covered Incentives

In order to qualify for the CHIPS Manufacturing Incentives Program in NOFO 1 and NOFO 2, applicants must submit a letter demonstrating that the state or local jurisdiction where the project is located has offered the applicant a “covered incentive.” Covered incentives are intended to attract the construction, expansion, or modernization of the proposed commercial fabrication or supplier facility. There is no mandated amount or form of covered incentives required by the NOFOs, but the Department encourages project incentive packages that create spillover benefits for the region (e.g., workforce development, infrastructure). The CHIPS Program Office has indicated it will evaluate covered incentives without potential for spillover benefits less favorably.

Additional Guidance on Covered Incentives
	Covered incentives can take a variety of forms, including workforce training grants, property concessions, R&D funding
	Contingent incentives are permitted provided that contingencies are clearly specified in the application
	Covered incentives committed prior to the NOFO release are eligible with approval from the CHIPS Program Office
	The CHIPS Program Office will not help companies obtain state and local incentives but does assess eligibility